1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor memory device, and more particularly to a process for fabricating a DRAM having a stacked-type capacitor comprising a cylindrical storage node electrode.
2. Description of the Related Art
The most widely employed capacitor structure for present day DRAMs is a stacked-type capacitor structure. A stacked-type capacitor having a cylindrical storage node electrode is known in the art. A conventional process of fabricating a cylindrical storage node electrode is disclosed, for example, in Japanese Patent Laid-Open No. S62-48062. The process of fabricating a DRAM having a stacked-type capacitor having a cylindrical storage node electrode disclosed in the above mentioned patent specification is described below by reference to FIGS. 1a to 1e. FIGS. 1a to 1e illustrate cross sectional views for a fabricating process for a semiconductor memory device in accordance with the prior art.
First, as shown FIG. 1a, a field oxide film 2 is formed on the surface of a p-type silicon substrate 1, and then a MOS transistor comprising a gate oxide film 3, gate electrode 4 serving also as a word line, a n.sup.+ source region 5a, and a n.sup.+ drain region 5b is constructed thereon. An interlayer insulating film 6b, at least a surface of which is made of a material other than a silicon oxide film, is deposited over the entire surface of the wafer by a CVD technique. A node contact hole 7 exposing n.sup.+ drain region 5b is opened in this interlayer insulating film 6b. Over the entire surface of the wafer an undoped polysilicon film is deposited by a CVD technique. Then, the undoped polysilicon film is ion-implanted or thermally diffused with a dopant, such as phosphorus, to obtain a n.sup.+ polysilicon film. Over the entire surface of the wafer a silicon oxide film of a specified thickness is deposited by a CVD technique. Using a patterned photoresist film 10 as a mask covering at least the area just above the node contact hole 7, the silicon oxide film and then the n.sup.+ polysilicon film are anisotropically etched to form a core 9b and a bottom electrode 8a, respectively.
In the next step, as shown FIG. 1b, after removing photoresist film 10, an undoped polysilicon film is formed on the entire wafer surface by a CVD technique and then doped to obtain a n.sup.+ polysilicon film 31 by ion implantation or thermal diffusion of phosphorus. Etch back of the n.sup.+ polysilicon film 31 follows, as shown FIG. 1C, leaving only on a sidewall of core 9b to form a cylindrical electrode 31a of a n.sup.+ polysilicon film. Thereafter, as shown FIG. 1d, core 9b is removed, for example, by wet etching with a buffered hydrofluoric acid, to thereby form a cylindrical storage node electrode having a bottom electrode 8a and a cylindrical electrode 31a. As shown FIG. 1e, dielectric film 13 and a cell plate electrode 14 are subsequently formed to complete a stacked-type capacitor having a cylindrical storage node electrode.
In the above mentioned process, the cylindrical electrode 31a, a part of the cylindrical storage node electrode, is formed by etch back, for example, by reactive ion etching (RIE). The resulting height of cylindrical electrode 31a depends on the height of core 9b and also on the etch back time needed to completely expose the surface of interlayer insulating film 6b and core 9b determines the uniformity of the cylindrical electrode 31a. Thus, if the etch rate of n.sup.+ polysilicon film 31 is uniform and the height of core 9b is uniform, then the height of cylindrical electrode 31a will be uniform.
Practically, however, the etching rate varies within the same silicon wafer in a range of about .+-.5% furthermore the height of core 9b has a variation of about .+-.5%. These variations result in nonuniformity in the height of cylindrical electrode 31a within the same semiconductor memory device, which results in variation of the surface area of the storage node. This in turn results in variation of the storage capacitance among memory cells, which causes unstable circuit operation such as degradation of the electrical characteristics of a power supply voltage margin or noise margin, etc.